The present invention relates to non-volatile memory cells, and particularly to floating-gate non-volatile memory cells. The present invention is most relevant to EPROMs, but could also be applied to related memory device types, such as EEPROMs.
FIGS. 1A and 1B show examples of EPROM device structures which have been previously discussed. FIG. 1A shows a device with planarized source and drain regions, and FIG. 1B shows an "advanced array" device with buried source and drain regions, invented at Texas Instruments (see e.g., issued U.S. Pat. Nos. 4,151,021, 4,184,207, and 4,373,248, which are hereby incorporated by reference).
EPROM cells are normally programmed by applying large positive voltages to control gate 10 and also to one of the source/drain diffusions 14 (which acts as the drain), so that hot electrons are generated and injected through the oxide 11 into the floating gate 12. During the programmation operation, a typical set of applied voltages might be: gate voltage V.sub.G =12.5 Volts; source voltage V.sub.S =0.5 Volt; and drain voltage V.sub.D =10 volts. Hot electrons will be generated by the currents passing through high electric field regions, and some of these hot electrons will pass through the gate oxide into the floating gate. ("Hot electrons" are electrons which have more energy than is required for them to reach the conduction band. The energy of some of these carriers may be larger than the conduction band minimum of silicon dioxide, so that (until these carriers lose their excess energy by scattering processes) they can travel freely through a dielectric, unlike ordinary electrons.)
Since the floating gate is insulated, it will hold the charge thus injected for long periods of time. Since the floating gate is interposed between the control gate and the channel of the device, the charge on the floating gate will have a partial screening effect which causes the apparent V.sub.T of the transistor (as seen by the control gate) to change. Thus, a non-disturbing read operation can be performed by applying a read voltage to the control gate which is sufficient to turn on only those floating-gate transistors which do not have substantial charge stored on their floating gates. For example, the read voltages used might by V.sub.D =1.5, V.sub.G =3, V.sub.S =0.
EEPROMs use essentially the same read operation, but their programmation operation differs in that charge injection into the floating gate is performed using merely electric-field enhanced tunneling through a thin dielectric into the floating gate. Thus, during programmation of an EEPROM the source and drain will normally be held at approximately the same voltage, since hot carrier generation is not needed.
One of the key factors which is sought to be optimized in any floating gate memory device is the programming time. EPROMs and EEPROMs are fast-read, slow-write devices, and most system applications using them will perform write operations only infrequently, but when writing is too slow it can become a major detriment to system efficiency even in these kinds of applications. For example, at the programming speed specifications commonly accepted in merchant 64K EPROMs, a megabit EPROM would take 14 minutes to program. Thus, successive generations have had successively tighter specifications on programming time.
Since EPROM programming is done by hot electron injection, relatively large electric fields must be created in the semiconductor channel region to accomplish this. This in turn means that relatively high voltages must be used to generate these high electric fields. Moreover, there is a trade off between programming voltage and programming time; use of excessively high voltages on chip presents dangers of catastrophic breakdown, as well as requiring the overhead to generate and transmit these high voltages; but, if a lower programming voltage is used for a given device structure, the programming time will increase. Relatively slow programming times are commonly accepted in floating-gate memories, but it is always desirable to increase the speed of programmation.
One advantage of the present invention is that faster EPROM programmation is provided. In particular, for a given applied voltage between gate and source/drain, the present invention provides faster programmation than would otherwise be available.
Another problem of prior EPROM devices is the "bipolar effect." See Mueller et al., "Short-Channel MOS Transistors in the Avalanche-Multiplication Regime." 29 IEEE Transactions on Electron Devices 1778 (1982), which is hereby incorporated by reference. That is, the npn parasitic bipolar device (defined by the n-type source, the p-type substrate, and the n-type drain) may turn on during the programmation operation and effectively bring programmation to a halt. The programming conditions are designed to produce hot electrons, and some of these hot electrons will collide with atoms in the lattice to produce additional carriers. For example, one hot electron, after a collision event, may generate two electrons plus one hole. Under the applied electric field, the hole that is generated is likely to flow into the substrate near the source junction, and the density of this hole current can be high enough that its space charge will forward bias the source/substrate junction, which then operates as an emitter/base junction to emit electrons.
This is particularly a problem with the advanced array type transistor as shown in FIG. 1B, since, in these transistors, there is no thick field oxide laterally separating transistors, so the parasitic bipolar device has a tremendous effective width, and may conduct current all down one column once it turns on.
FIG. 9 shows two I-V curves for a sample EPROM cell. Curve 902 shows the I-V characteristics of the cell while it is being programmed. On this curve, the steep portion 901 shows the turn-on regime, and the relatively flat portion 903 shows the regime of saturated channel current, the region 904 of steeply declining current shows the regime where hot electron injection into the gate is occurring (and dynamically shifting the threshold voltage, and therefore reducing the current for a given drain voltage), and the portion 905 shows the regime where parasitic bipolar current becomes important. The operating point for programmation is typically selected at a higher drain voltage than is strictly necessary to reach the portion 904, to permit faster programmation. Another advantage of the present invention is that, since the parasitic bipolar turns on at a higher drain voltage, the programmation operating point 907 can optionally be selected higher on the I-V curve portion 905, i.e., higher voltages can optionally be used to achieve even more improvement in programming speed. The second I-V curve 906 shows (for comparison) the I-V characteristics of an EPROM cell after programmation.
A related parameter of the programming operation is the reliability of programmation. That is, even if the programming time of each bit is reasonably fast, a key parameter to the user is the net programming time. Prior devices will commonly achieve much less than 100% programmation per pass, and this lengthens programming time greatly. For example, if 90% of all bits program successfully on each pass, then a megabit memory would be expected to take six full programming cycles to complete programmation. The need for multiple program/read/reprogram cycles (known as "bit-banging") is heartily disliked by users.
Another constraint on EPROM device fabrication is that the substrate doping must be selected to accommodate the peripheral devices as well as the floating-gate transistors in the memory array. This means that if the substrate background doping concentration is simply increased to reduce the bipolar effect, then the peripheral devices will suffer increased body effect, which is undesirable, as well as greater parasitic capacitance to substrate, lower junction breakdown voltages, and increased leakage currents. Avoidance of these factors is particularly desirable where the peripheral circuits are CMOS, i.e., use both NMOS and PMOS transistors to conserve power.
The present invention improves all of these factors simultaneously, without seriously impeding fabrication of the cell.
The present invention provides an improved floating-gate transistor, with a different doping profile. In addition to the background p-well doping, and V.sub.T -adjust doping to set the desired threshold voltage, the present invention also provides increased p-type doping below the channel and laterally adjacent to the source/drain diffusions. Preferably this is done by using two implants of opposite type at the stage when V.sub.T -adjust implant of the floating-gate transistors in the memory array would normally be performed, namely both a p-type implant to provide the increased shallow p-type doping and a very shallow n-type implant of a low-diffusivity species, such as arsenic. Thus the doping at the surface of the channel (which defines the threshold voltage) can be kept to the desired level for threshold voltage control, but the dopant concentration below the channel and laterally adjacent to the source/drain diffusions will be substantially higher than the channel or substrate dopings. The increased doping at the drain boundary will cause increased hot electron generation, which means that faster programmation will be provided for a given applied voltage.
Thus, one key advantage of the present invention is increased hot electron generation during programmation, which means that faster programmation will be provided for a given applied voltage.
A further advantage of the present invention is that the action of the parasitic lateral bipolar transistor will be suppressed, since the space charge density of the additional ionized dopants introduced by the additional boron doping immediately below the channel will cause more of the electrons emitted at the source/substrate junction to diffuse upward into the channel (where they are actually beneficial), rather than diffusing laterally to cause the onset of bipolar action. Thus, since the bipolar effect is suppressed, the programming efficiency is therefore higher.
A further advantage of the present invention is that the device qualities of the transistors in the periphery need not be degraded by increased substrate doping.
Another advantage of the present invention is believed to be that, while hot electron generation is enhanced during the write operation, it is not substantially increased during the read operation, and therefore data retention is not degraded by the improvement in write speed.
Note that the Mueller article cited above also discusses the utility of increased p-type doping below the channel in reducing the "bipolar effect." The "type B" process described on page 1779 uses a very deep implant (1.2E12 cm.sup.-2 of (presumably) boron at 140 keV) to achieve a dopant profile, as shown in FIG. 2, which peaks below the surface. (This doping profile is probably not directly comparable to the profile shown as FIG. 10, since it is not clear that the Mueller article is showing as-annealed profiles; the doping peak is shown at about the depth where the as-implanted peak of a 140 keV implant would be expected to fall, and therefore these may be as-implanted profiles or inaccurately modeled simulations of as-annealed profiles.) However, it is clear that the example of FIG. 10 shows a substantially higher peak doping at a substantially shallower depth than any teaching of the Mueller et al. article. The Mueller et al. article is not seen to contain any suggestion of an n-type V.sub.T implant together with a p-type implant, nor is it seen to contain any suggestion of optimizing the doping profiles of the NMOS peripheral transistors differently from those of the array transistors; nor is it seen to contain any teaching of the criticality of the relation between peak doping depth and source/drain diffusion depth. The present invention goes beyond the teachings of the Mueller et al. article in these respects and others, and as a result provides substantial advantages. For example, the present invention permits the memory transistors and the PMOS and NMOS peripheral transistors to all have separately optimized doping profiles, with a minimum cost in process steps. The use of a low-diffusivity n-type counterdopant means that the peak p-type doping concentration in the memory transistors can be located closer to the surface, and this in turn means that advantages of increased programming speed (due to increased hot electron generation) result.
The V.sub.T -adjust implants of the memory array are preferably done after any required high temperature steps, specifically after field oxidation (or thick field oxide growth) to minimize the integral of .sqroot.Dt and therefore permit the peak of the boron compensating implant to occur close to the surface.
Arsenic is preferred for the V.sub.T -adjust implant, to minimize its integral .sqroot.Dt by minimizing D. That is, in the presently preferred embodiment the boron implant has only a slightly longer stopping distance than the arsenic implant (roughly 1100 .ANG. for the boron and 850 .ANG. for the arsenic); however, the difference in their diffusivities means that subsequent diffusion will further shift the boron profile relative to the arsenic profile. The final dopant profiles--i.e. the profiles in the finished device--are what determine the device characteristics, and the presently preferred embodiment provides final dopant profiles such that EQU x.sub.B.sbsb.-50% &gt;2x.sub.As.sbsb.-50%.
i.e. the boron concentration is 50% less than its peak value at a depth more than twice the depth where the arsenic concentration is 50% less than its peak value. More particularly, it is also preferred that EQU 2x.sub.j &gt;x.sub.B.sbsb.-50% &gt;2x.sub.As.sbsb.-50%.
i.e. that the boron concentration has tapered off to half its maximum at a depth less than twice the depth of the source/drain bottom junction.
Another teaching of the present invention regarding final dopant profiles is that n.sub.max(x.ltoreq.0.5 .mu.m) (the largest value of the net p-type dopant concentration anywhere within the volume extending from 0 to 0.5 microns below the gate oxide/channel interface) is more than 1.5 times n.sub.chan (the net p-type dopant concentration in the channel at the gate oxide/channel interface): ##EQU1## Preferably, n.sub.max(x.ltoreq.0.5 .mu.m) is more than 1.5 times n.sub.chan and is also more than twice n.sub.sub (the net p-type background dopant concentration in the substrate): ##EQU2##
Once these teachings of the present invention are appreciated, it may be seen that other processing sequences could be used to achieve the desired dopant profile as taught by the present invention.
For example, antimony could be used for the shallow n-type implant which adjusts V.sub.T. Even phosphorus could be used instead, although in that case a higher implant energy would be used for the boron implant, to assure that increased net p-type doping occurred below the channel as discussed above. Similarly, those skilled in the art can easily configure a wide range of implant dose, implant energy, and annealing time and temperature specifications which will provide the structure taught by the present invention by various routes, although there are particular advantages to the specific preferred process embodiments claimed.
FIG. 10 shows the doping profiles achieved (in one embodiment of the invention) for the NMOS peripheral transistors (curve 102) and for the floating-gate memory transistors (curve 104). Separate profiles are also broken out for the atomic boron concentration n.sub.B (curve 106) and for the atomic arsenic concentration (curve 108). Note that the boron concentration profile is compensated at shallow depths (in this example, down to about 0.2 microns below the gate oxide), so that the surface concentration is reduced to the level desired to set the "erase V.sub.T " i.e. the V.sub.T of a cell which has not been programmed) of the memory cells.
Note that the curve 102 shows a slightly increased doping level at the surface to set the V.sub.T of the NMOS peripheral transistors to a desired level. This points up to an important further advantage of the invention: it is normally necessary in an EPROM process, to set the surface doping concentration differently for the NMOS peripheral transistors and for the memory transistors. That is, a simple mask level must be used anyway to pattern the different threshold implants, so the mask used (in the presently preferred embodiments) to apply the arsenic V.sub.T implant to the memory transistors only does not actually cost an additional masking step.